smu assignment of Bsc IT 1st sem Logic design

                                         Fall 2014, ASSIGNMENT

PROGRAM	BSC IT
SEMESTER	I
SUBJECT CODE & NAME	BT0064, LOGIC DESIGN

Q NO.1 Solve each of the following 4-bit subtraction problems using 2's complement representation.

i.                     (00110)2 – (00101)2

     ii.         (01100)2 – (01010)2

     iii.         (1011)2 - (1001)2

     iv.         (0111)2 - (0001)2

     v.          (0010)2 – (1000)2

Answer:

i.                   (00001)        

ii.                  (00010)

iii.               (0010)

iv.              (0110)

v.                 (0010)

Q NO.2 Draw the symbol for XNOR & X-OR and explain the truth table?

Answer:

       Military XOR symbol

The XOR gate (sometime EOR gate) is a digital logic gate that implements exclusive disjunction- it behaves according to the truth table to the right. If either one of the input is HIGH, then the output will be HIGH. The output of the gate results a LOW value when either the inputs of the gate are LOW or both are HIGH.

This function is addition modulo 2. In digital system the binary adder are implemented using XOP gate. A half adder consists of an XOR gate and an AND gate.

         

   

          INPUT               OUTPUT

          A      B                AXORB

           0      0                    0

           0      1                    1

           1      0                    1

           1      1                    0

Rectangular XOR symbol

X-NOR Gate

 

       Military X-NOR symbol

The XNOR gate is a digital logic gate whose function is the inverse of the exclusive OR (XOR) gate. The two-input version implements logical equality, behaving according to the truth table to the right. If the inputs to XOR gate are same, then the output will be HIGH. A LOW output will result if both the inputs to the XOR gate are not same.

 

          INPUT             OUTPUT

          A      B               AXORB

           0      0                    1

           0      1                    0

           1      0                    0

           1      1                    1

Rectangular X-NOR symbol

Q NO.3 What are adders? Explain half adders and full adders with circuit diagrams.

Answer: ADDERS

There are two types of single bit adders. They are Half adder and Full adder.

A half adder circuits will generates sum S and carry C from the two of its input A and B. Sum S can generated by XORing inputs A and B and Carry C is generated by ANDing A and B. The output of the half adder will be of 2 bits with sum is determined from least significant bit and carry is determined from most significant bit.

A full adder circuits adds the carry in C along with the two inputs A and B. A large adder circuit can be constructed using multiple full adders. In full adder circuit, carry in is labeled as Ci and Cin and carry out is labeled a Co or Cout, labling this way will remove the ambiguity between the output carry and the input carry.   

Half adder

A half adder is a digital circuit which accepts two inputs and performs addition on them and generates two binary digits known as sum and carry.

As the carry is not included in the addition, this circuits cannot be used to perform addition of multiple numbers.

     Half adder circuit diagram

Following is the logic table for a half adder.

A      B       C        S

0       0        0         0

0       1        0         1

1       0        0         1

1       1        1         0

Full adder

      Full adder circuit diagram

Inputs:{A, B, CarryIn} à Outputs:{Sum,CarryOut}

Schematic symbol for a 1-bit full adder

Cout  = ( A . B ) + ( Cin . ( A + B ) + ( Cin . B ) + ( Cin . A )

A full adder circuits adds the carry in C along with the two inputs A and B. the full adder performs addition on 3 input bits and generates carry and sum binary output. Multiple outputs full adders can be performs the addition of multiple binary inputs.

Q NO.4 What is ring counter? Explain it working with the help of diagram.

Answer: A ring counter can be constructed using a SISO(serial-in serial-out) shift register by connecting by the output of the last stage to the input of the first stage directly, thus forming a ring or loop. All but one flip-flip in a ring counter will be in the same state which could be either 0 and 1. If the state of that single flip-flop is chosen to be 1, then the valid states of the a 4 bit ring counter are 1000, 0100, 0010 etc. if we choose 0 as the state of differing flip-flop then the equivalent valid states would be 0111, 1011,1101. The states of the single flip-flop which differs from the rest is shifted on every clock cycle.

An example of a 4 bit ring counter constructed using S-R(set- reset) flip-flops is shown below(A: Logic diagram). Output of each stages is fed to the R (reset) input to the current stages. The wave form of the flip-flops FF1 through FF4 in response to the clock signal on ‘INPUT’ is shown next (B: Timing Diagram).

                           A: Logic diagram B: Timing Diagram

The operation of the circuits is straight forward. Assumes that the initial output of first flip-flop is 1 and reset of the flip-flops and ‘INPUT’ are at 0. This means that A will be at 1 and B, C and D will be at 0. We can say that the counter state now is 1000. The Q output of first flip-flop is also connected to the B input of the first AND gate.

Let us apply a logic 1 to the ‘INPUT’ line which is connected to A inputs of all the AND gates. We know that as output (Q) of FF2 TO FF4 are low, output of AND gates 2,3,4 will be 0. But the output of AND gate 1 is HIGH (1) as both of its inputs are at 1 and A, C, D output will be at logic 0. Please note that in the process, the counter state now is 0100. Now if we apply one more pulse to the ‘INPUT’ line again, the same process repeats and the counter states would be 0010.

                                                       

              Ring counter

         Input                         Output

         A     B        Ci           Co     S

          0     0          0             0      0

          0     0          1             0      1

          0     1          0             0      1

          0     1          1             1      0

          1     0          0             0      1

          1     0          1             1      0

          1     1          0             1      0

          1     1          1             1      1

From the above discussion it can be observed that between OR gate and XOR gate there is only one discrepancy when inputs are, therefore without changing the resulting logic the OR gate at carry out can be replaced with an XOR gate. If the circuits is implemented on the common chips, it will be more convenient to use only two gates.

Two half adder circuits can be used to implement a full adder circuits, the two inputs A and B are connected to one half adder and its output sum is connected as input to the second half adder and two carry outputs are ORed. The Boolean function for S can be expressed as XOR of three inputs A, B, Ci and a majority function of A, B, and Ci can be Carry out equation. Sum of three on bit numbers will be the output of the full adder circuit.

Q NO.5 Explain any five types of digital to analog convertors.

Answer:

The most common types of electronics DACs are:

·        Pulse Width Modulator is the simplest type of DAC. A low pas analog filter with a duration specified by the digital input is used. A stable current or voltage is passed into the filter. This is commonly used technique in speed control of electric motor and is now commonly used in high fidelity audio application.

·        Oversampling DACs or Interpolating DACs such as the Delta-Sigma DACs, use a technique termed pulse density conversion. Use of lower resolution DAC is allowed because of the usage of the oversampling technique. As the oversampled result is inherently linear, a sample 1-bit DAC is often selected. In a technique named delta-sigma modulation. DAC is driven with a pulse density modulated signal which is created with step non-linearity, negative feedback loop and a low pass filter. In effect, quantization noise gets high pass filtered and thus driving the noise out of the low frequencies in to the high frequencies which is of little interest. This technique is called noise shaping. An analog low-pass filter at the output removes the quantization noise at the high frequencies. Due to high linearity and low cost, most of the very high resolution DACs is of this type. Increased oversampling rete can reduce the specification overhead on the low pass filter and support further reduction of the quantization noise. Delta sigma DACs make resolution of 24-bits and speed greater than 100 thousand samples per second achievable. A 1-bit DACs with a simple first-order integrator would have to run at 3 THz with a higher order low-pas filter in the noise-shaping loop to achieve 24 meaningful bits to resolution. A first order delta-sigma modulator can be constructed with an integrator which is essentially a low pas filter with frequency response inversely proportional to frequency. Higher degrees of noise-shaping are achieved by using multiple higher order topologies with a stable topology.

·        Binary weighted DAC is constructed with one resister and a current source for bit of the DAC connected to a summing point. Correct output value is the sum of these precise of each individual voltage or current counts for the accuracy of the final output. But this one of the fastest converters. This type of converters is normally limited to 8-bit resolution or less as the high-precision resistor and current sources are expansive.

·        R-2R Ladder ADC is a binary weighted DAC in which registers of values R and 2R are repeatedly cascaded. Due to the easiness in producing equal valued resistors, precision is high for this kind type of converters. But a RC-constants increases for each R-2R link, converter performances is slow.

·        Thermometer coded DAC makes use of equal resistor or current source segment for each of the values the DAC output can possibly take. A 10-bit thermometer will have 1024 segments and a 5-bit thermometer will have 32 segments. Even though it is costly, this may be the fastest and highest precision DAC implementation.

Q NO. 6 What are shift registers? Explain serial in serial out shift register.

Answer: Shift registers, like counters, are a form of sequential logic. Sequential logic, unlike combinational logic is not only affected by the present inputs, but also, by the prior history. In other words, sequential logic remembers past events.

Shift registers produce a discrete delay of a digital signal or waveform. A waveform synchronized to a clock, a repeating square wave, is delayed by "n" discrete clock times, where "n" is the number of shift register stages. Thus, a four stage shift register delays "data in" by four clocks to "data out". The stages in a shift register are delay stages, typically type "D" Flip-Flops or type "JK" Flip-flops.

Formerly, very long (several hundred stages) shift registers served as digital memory. This obsolete application is reminiscent of the acoustic mercury delay lines used as early computer memory.

Serial data transmission, over a distance of meters to kilometers, uses shift registers to convert parallel data to serial form. Serial data communications replaces many slow parallel data wires with a single serial high speed circuit.

Serial data over shorter distances of tens of centimeters, uses shift registers to get data into and out of microprocessors. Numerous peripherals, including analog to digital converters, digital to analog converters, display drivers, and memory, use shift registers to reduce the amount of wiring in circuit boards.

Some specialized counter circuits actually use shift registers to generate repeating waveforms. Longer shift registers, with the help of feedback generate patterns so long that they look like random noise, pseudo-noise.

Basic shift registers are classified by structure according to the following types:

·        Serial-in/serial-out

·        Parallel-in/serial-out

·        Serial-in/parallel-out

·        Universal parallel-in/parallel-out

·        Ring counter

Serial-in Serial-out shift register(SISO)

Above we show a block diagram of a serial-in/serial-out shift register, which is 4-stages long. Data at the input will be delayed by four clock periods from the input to the output of the shift register.

Data at "data in", above, will be present at the Stage A output after the first clock pulse. After the second pulse stage A data is transferred to stage B output, and "data in" is transferred to stage A output. After the third clock, stage C is replaced by stage B; stage B is replaced by stage A; and stage A is replaced by "data in". After the fourth clock, the data originally present at "data in" is at stage D, "output". The "first in" data is "first out" as it is shifted from "data in" to "data out".

Made By Raju Thakur                                                           Roll No:  1408015349